A Buffer-aware Routing Algorithm for Irregular 2-D Network-on-Chip without Virtual Channel

Network-on-Chips (NoCs) usually use regular mesh-based topologies. Regular mesh topologies are not always efficient because of power and area constraints which should be considered in designing system-on-chips. To overcome this problem, irregular mesh NoCs are used for which the design of routing algorithms is an important issue. This paper introduces a routing algorithm for irregular mesh-based NoCs called IIR for Mesh Networks. In contrast to other routing algorithms, this algorithm can be implemented on any arbitrary irregular mesh NoC and can tolerate solid irregular areas without using virtual channels. Moreover, the proposed algorithm can tolerate non-overlapping faulty regions. Further-more, the proposed scheme misroutes messages both clockwise and counter clock-wise directions to reduce channel contention on an oversized node (ON). The main idea of this algorithm borrowed from odd-even turn model and FT-Cube algorithm. Additionally, proposed algorithm is deadlock-free and livelock-free in meshes for non-overlapping multiple irregular areas and faulty regions in NoC interconnection network. IIR algorithm increases the throughput of physical links more than FTR with lower average message delay. As the simulation results show, IIR has a higher performance compared to FTR algorithm. The results also show that our algorithm has better performance with 100% traffic load in Network-on-Chip.